2000 Mar 28
2
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351TS
CONTENTS
1
FEATURES
1.1
General
1.2
Control
1.3
IEC 958 input
1.4
Digital sound processing and DAC
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
Clock regeneration and lock detection
8.2
Mute
8.3
Auto mute
8.4
Data path
8.4.1
IEC 958 input
8.4.2
Audio feature processor
8.4.3
Interpolator
8.4.4
Noise shaper
8.4.5
The Filter Stream DAC (FSDAC)
8.5
Control
8.5.1
Static pin control mode
8.5.2
L3 control mode
8.6
L3 interface
8.6.1
General
8.6.2
Device addressing
8.6.3
Register addressing
8.6.4
Data write mode
8.6.5
Data read mode
8.6.6
initialization string
8.6.7
Overview of L3 interface registers
8.6.8
Writable registers
8.6.9
Readable registers
9
LIMITING VALUES
10
THERMAL CHARACTERISTICS
11
CHARACTERISTICS
12
TIMING CHARACTERISTICS
13
APPLICATION INFORMATION
14
PACKAGE OUTLINE
15
SOLDERING
15.1
Introduction to soldering surface mount
packages
15.2
Reflow soldering
15.3
Wave soldering
15.4
Manual soldering
15.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
16
DEFINITIONS
17
LIFE SUPPORT APPLICATIONS
2000 Mar 28
3
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351TS
1
FEATURES
1.1
General
2.7 to 3.6 V power supply
Integrated digital filter and Digital-to-Analog Converter
(DAC)
Master-mode data output and input interface for off-chip
sound processing
256f
s
system clock output
20-bit data path in interpolator
High performance
No analog post filtering required for DAC
Support sampling frequencies from 28 kHz up
to 100 kHz
The UDA1351TS is fully pin and function compatible
with the UDA1350ATS.
1.2
Control
Controlled either by means of static pins or via the
L3 microcontroller interface.
1.3
IEC 958 input
On-chip amplifier for converting IEC 958 input to CMOS
levels
Lock indication signal available on pin LOCK
Lock indication signal combined on-chip with the Pulse
Code Modulation (PCM) status bit; when non-PCM is
detected, pin LOCK indicates out-of-lock
Key channel-status bits available via L3 interface (lock,
pre-emphasis, audio sample frequency, two channel
PCM indication and clock accuracy).
1.4
Digital sound processing and DAC
Automatic de-emphasis when using IEC 958 input with
32.0, 44.1 and 48.0 kHz audio sample frequencies
Soft mute by means of a cosine roll-off circuit selectable
via pin MUTE or the L3 interface
dB linear volume control with 1 dB steps from 0 dB to
-
60 dB and
-
dB
Bass boost and treble control in L3 control mode
Interpolating filter (f
s
to 128f
s
) by means of a cascade of
a recursive filter and a FIR filter
Third order noise shaper operating at 128f
s
generates
the bitstream for the DAC
Filter Stream DAC (FSDAC).
2
APPLICATIONS
Digital audio systems.
3
GENERAL DESCRIPTION
Available in two versions:
UDA1351TS:
only IEC 958 input to DAC in SSOP28 package.
UDA1351H:
full featured version in QFP44 package.
The UDA1351TS is a single chip IEC 958 audio decoder
with an integrated stereo DAC employing bitstream
conversion techniques.
A lock indication signal is available on pin LOCK,
indicating that the IEC 958 decoder is locked. This pin is
also used to indicate whether PCM data is applied to the
input or not. When non-PCM data is detected, the device
indicates out-of-lock.
By default, the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overruled in the L3 control mode.
2000 Mar 28
4
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351TS
4
QUICK REFERENCE DATA
Note
1. The output voltage of the DAC is proportional to the DAC power supply voltage.
5
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DDD
digital supply voltage
2.7
3.0
3.6
V
V
DDA
analog supply voltage
2.7
3.0
3.6
V
I
DDA(DAC)
analog supply current of DAC
power-on
-
8.0
-
mA
power-down
-
750
-
A
I
DDA(PLL)
analog supply current of PLL
at 48 kHz
-
0.7
-
mA
at 96 kHz
-
1.0
-
mA
I
DDD(C)
digital supply current of core
at 48 kHz
-
16.0
-
mA
at 96 kHz
-
24.5
-
mA
I
DDD
digital supply current
at 48 kHz
-
2.0
-
mA
at 96 kHz
-
3.0
-
mA
P
power consumption at 48 kHz DAC in playback mode
-
80
-
mW
DAC in Power-down mode
-
58
-
mW
power consumption at 96 kHz DAC in playback mode
-
109
-
mW
DAC in Power-down mode
-
87
-
mW
General
t
rst
reset active time
-
250
-
s
T
amb
ambient temperature
-
40
-
+85
C
Digital-to-analog converter
V
o(rms)
output voltage (RMS value)
note 1
-
900
-
mV
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
f
i
= 1.0 kHz tone at 48 kHz
at 0 dB
-
-
90
-
85
dB
at
-
40 dB; A-weighted
-
-
60
-
55
dB
f
i
= 1.0 kHz tone at 96 kHz
at 0 dB
-
-
85
-
80
dB
at
-
40 dB; A-weighted
-
-
57
-
52
dB
S/N
signal-to-noise ratio at 48 kHz f
i
= 1.0 kHz tone; code = 0; A-weighted 95
100
-
dB
signal-to-noise ratio at 96 kHz f
i
= 1.0 kHz tone; code = 0; A-weighted 95
100
-
dB
cs
channel separation
f
i
= 1.0 kHz tone
-
96
-
dB
V
o
unbalance of output voltages
f
i
= 1.0 kHz tone
-
0.1
0.4
dB
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1351TS
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
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